CAREER: Robust Design for Scaled CMOS Technologies

Stanford University, Stanford CA

Investigators

Abstract

Prop No: 0643319 Title: CAREER:Robust Design for Scaled CMOS Technologies PI: Subhasish Mitra Inst: Stanford University Abstract This project focuses on creating novel core technologies for designing robust computing and communication systems, and educating future generations of engineers who will be responsible for designing such systems with robustness as a fundamental design objective. Such systems constitute an inseparable part of human lives today, and will be further integrated in the future over a wide range of complex applications such as information appliances, transportation, health, bio-medical, and finance. The project is motivated by an imminent paradigm shift in hardware design resulting from the growing problem of hardware failures in future semiconductor process technologies. The traditional hardware design paradigm assumes that semiconductor process technologies always produce perfect hardware that will never operate incorrectly during its lifetime. Continuous push for smaller semiconductor process geometries also called technology scaling which is the key to the success of the semiconductor industry is approaching a point where such a design paradigm will be infeasible due to fundamental limitations. This project breaks this barrier by adopting the following principle: accept the fact that the underlying hardware will be imperfect, and develop technologies and tools for designing efficient, cost-effective, and failure-aware robust systems that ensure high quality of service, data integrity, availability, security and safety. This advancement in Computer Engineering will enable the semiconductor industry to continue technology scaling with immense impact on future electronic products. It is also expected that the research ideas developed in this project will have a far-reaching impact on robust designs in emerging revolutionary nanotechnologies far beyond contemporary CMOS technologies.