Interconnect Networks for Three-Dimensional Gigascale System-on-a-Chip

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

NSF Proposal 0701560 M. Bakir & J. Meindl The objective of this research is to develop the interconnect networks needed to enable a three-dimensional integrated gigascale system-on-a-chip. The approach is to perform experimental research and derive physical models to define the limits and opportunities of fully compatible electrical, optical, and fluidic (or trimodal) input/output and trimodal through-wafer interconnects. The overarching strategy of the research is to extend and utilize silicon wafer-level batch fabrication technology, the key to the success of silicon technology, to the development of the trimodal interconnect networks. The intellectual merit of the proposed research is to transcend current silicon ancillary technologies and thinking through high-risk and high-payoff research in the area of interconnect technologies for power delivery, high input/output bandwidth, and heat removal and to enable the most compact and highest performance three-dimensional gigascale system. The broader impact resulting from this highly-interdisciplinary research will be the enabling of the semiconductor industry to greatly exceed the heat removal, input/output bandwidth, and power delivery metrics for high performance chips at the 14 nm node (year 2020) as projected by the International Technology Roadmap for Semiconductors. The input/output interconnect technologies will be based on simple and affordable fabrication processes thereby making them accessible to a much wider range of researchers and small companies around the world. As a node within the National Nanotechnology Infrastructure Network program, we plan to bring and expose high-school students and minorities to results from this research as we have done in the past to encourage them to pursue science and engineering