CAREER: Semantics and Hardware Implementation of Transactional Memory

University Of Pennsylvania, Philadelphia PA

Investigators

Abstract

After decades of research on shared-memory multiprocessors, computers with multiple processors have now been widely embraced with the arrival of the multicore revolution. Unlike the previous microprocessor revolution---which required no fundamental software changes---the multicore revolution requires a significant shift for software. Because much of the accustomed exponential performance improvements over the next decade will come directly from multiplying the number of processor cores on a chip, programmers that wish to harness this computational power must undertake the difficult task of creating parallel versions of their programs. To reduce the difficulty of this task of creating correct and efficient shared-memory programs, recent work on "transactional memory" has focused on providing the programmer with a higher-level primitive than just lock- based critical sections for managing concurrency in their shared-memory programs: a region of code annotated to execute as if it was not running in parallel with other code. Although conceptually serial, advanced implementations allow for concurrent execution while still providing a serializable semantics. The goal of this research is to identify, understand, and resolve the most important semantic and implementation challenges of hardware-based transactional memory. Just as the multiprocessor research successfully overcame important challenges, this research tackles the analogous challenges for hardware transactional memory: (i) understanding the semantics of the hardware/software interface, (ii) developing simple and fast hardware implementations, and (iii) creating critical experimental simulation and workload infrastructures.