Ultra High Performance Digital Circuit Design and Synthesis

University Of Texas At Dallas, Richardson TX

Investigators

Abstract

The focus of this proposal is on extremely high performance (very high speed, but also energy efficient) digital IC design. The proposed research has three tasks: 1) high performance digital logic techniques, 2) CAD tool development to aid rapid deployment of the high performance logic techniques, and 3) applications of the high performance logic techniques; in particular, the design of circuit blocks that demonstrate unprecedented speed, while still having reasonable energy efficiency Task 1: Research on High Performance Digital Logic Techniques: Focus is on maximizing the performance of the output prediction logic (OPL) technique, and developing yet faster and/or more energy efficient logic techniques. Task 2: CAD for Rapid Implementation of High Performance Digital Logic: Techniques Two CAD tools will be developed to ease design and verification of OPL circuits under this proposal: 1) A static timing analysis tool for OPL circuits, and 2) an automatic transistor/gate sizing tool for OPL circuits that minimizes energy consumption subject to delay goals. Also a powerful convex-optimization-based tool for automatic transistor and gate sizing for OPL circuits is being investigated. The tool will minimize energy consumption while achieving a specified delay target. Task 3: Research on Applications of High Performance Digital Logic Techniques: Applications include: 1) a new 64b adder architecture having a simulated worst-case delay (under severe process, voltage and temperature variations) of 3.3 fanout-of-four inverter delays. 2) a very fast floating-point divider with the possibility of a latency of 6ns for a 0.20-micron TSMC process. This divider will run at a frequency of at least 3 GHz in this 0.20-micron process, enabling the use of division for the very first time in signal processing and communications circuits. 3) a new FPGA architecture, called OPL-FPGA, which suggests an FPGA could approach the circuit speeds obtained by standard cell ASICs. Mapping common datapath circuits to this architecture further suggests that speedups of at least 3.3X over state-of-the-art commercial FPGAs are attainable.