Bistable Quantum Dot Gate Field-Effect Transistors Exhibiting Multi-State Operation: A Novel Approach to Reduce Device Count in ICs

University Of Connecticut, Storrs CT

Investigators

Abstract

Jain proposal Abstract Bistability in Sub-22nm Quantum Dot Gate FETs for Next Generation Analog and Digital Circuits The objective of this project is to develop a design and process to fabricate 22nm quantum dot-gate FETs. The approach is to first fabricate long-channel quantum dot (QD) gate FETs exhibiting controlled bistable characteristics using site-specific selfassembly processing technique to form QD gates. This will be followed by the design and simulation of 22 nm QD gate FET structures, and the development of a CMOScompatible fabrication process demonstrating QD gates. Another objective is to develop a SPICE model for QD gate FETs and simulate multiple valued logic (MVL) circuits, and analog circuits comprising QD FETs. The novelty of our quantum dot (QD) gate FET structures lies in their experimentally verified bistable behavior that results in three-state current-voltage transfer characteristics. Three-state logic provides new versatility in designing CMOS digital logic and memory circuits that would lead to significantly reduced FET counts. The proposed research will impact the silicon industry by providing a novel pathway to achieve digital and analog functionality using a reduced number of three-state FETs in comparison with conventional FETs. The continued development of site-specific selfassembly of nanocomposites will also benefit the emerging nanotechnology-based industry. It will strengthen the recently introduced Nanoscience and Nanotechnology courses (ECE 250, ENGR 251) in the undergraduate curriculum. This will trickle down to high school students working in our Micro/Optoelectronics Lab during the summer under the YESS (Young Science & Engineering Scholars) program (running over 10 years) and K-12 students (under the Bridge Program for underrepresented students).