SGER: Lithography- Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs

University Of Maryland, College Park, College Park MD

Investigators

Abstract

ABSTRACT 0634321 Ankur Srivastava U of Maryland - College Park NSF-SGER: Lithography-Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs Nanostructure graphite (carbon nanotubes and/or graphene nanostrips) has extraordinary properties (high carrier mobility, tunable bandgap, high thermal conductivity, high current capacity, lack of electromigration) that makes it a very promising candidate for solving existing problems in both the active layer and interconnect layers in CMOS. The proposed research will study the embedding of nanostructured graphite in the active or interconnect layers of conventional CMOS circuits. Specifically, we will: (1) develop a sound understanding of the silicon compatible fabrication process of CNTs and graphene strip transistors (a new invention in the field of nanostructured carbon), (2) develop a probabilistic model for predicting the variability in diameter, length, orientation, width etc., (3) using this model we will re-analyze the potential advantages of CNT transistors and interconnects and compare them with the advantages of graphene strip transistors. To this end we will study large scale CMOS transistor banks, power grid networks, clock trees and global busses (4) give a set of tolerences to fab-engineers which they need to achieve in their fabrication process for effective exploitation of carbon based nanotechnology embedded into silicon, and (5) develop a set of design rules which if the designers follow would result in a highly manufacturable layouts with both CNTs, graphene strips and traditional CMOS. The key novelty of our approach is the fact that a) we will explicitly compare carbon nanotubes and graphene transistors (a new invention in nanostructured carbon) b) we will explicitly consider the practical limitations of state of the art fabrication processes (unlike the current state of the art that does not take such imperfections into account) c) we will investigate their applicability on large scale CMOS/interconnect structures like transistor banks, clock trees, power grid meshes, etc rather than individual transistors and interconnects and therefore consider the challenges imposed by these specific large scale CMOS/interconnect structures. Intellectual Merit A significant intellectual merit of the proposal is the pairing of state-of-the-art design methodologies with data from real fabrication process and real experimental devices to tackle the problem of incorporation of graphite nanostructures in CMOS. This proposal brings together Srivastava with expertise in design automation and design methodologies, with Fuhrer, who has experimental expertise in carbon nanotube and graphene devices. For the first time large scale applicability of graphene strip transistors to silicon CMOS would be evaluated and compared with traditional carbon nanotubes. More so this evaluation would explicitly consider the fab limitations and imperfections. Finally, instead of focusing on micro scale integration problems, we will explicitly investigate large scale structures like power grids, clock trees, transistor banks and evaluate the applicability of nanostructured carbon. Such an analysis has not been done before. Broader Impacts The proposed research will lay the foundation for a larger study of incorporation of carbon nanostructures into CMOS which would be expended to include device prototyping and device-level and systems-level modeling. The proposed research will produce the first realistic studies of incorporating carbon nanostructures in CMOS, and will be instrumental in guiding research to the optimal areas of exploration in terms of carbon nanostructure fabrication, assembly, and characterization. Carbon nanostructures are very promising candidates for extending the semiconductor technology roadmap into the post-silicon era. The continued scaling of CMOS in this era will have enormous economic and societal benefits. Educational Impact The proposed research will begin a collaborative dialog between the design and nanoelectronics device communities. Two graduate students will receive interdisciplinary training at the forefront of nanoelectronics research.