CAREER: Physical Design Automation for Fast and Reliable 3D Circuits

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

CAREER: Physical Design Automation for Fast and Reliable 3D Circuits PI: Sung Kyu Lim, Georgia Institute of Technology The 3D integrated circuit is an emergent technology that vertically stacks multiple die with a die-to-die interconnect. The die-to-die via pitch is very small and provides the possibility of arranging digital functional blocks across multiple die at a very fine level of granularity. This results in a decrease in the overall wire length, which translates into less wire delay and less power. Advances in 3D integration and packaging are undoubtedly gaining momentum and have become of critical interest to the semiconductor community. These 3D integrated circuit and package manufacturing technologies are rapidly being adopted by several leading companies for commercial applications. In spite of the rapid advancement in 3D fabrication and packaging technologies, the design automation community has seen very little progress on the development of computer-aided design tools for 3D integration. The goal of this research is to develop physical design algorithms for 3D integrated circuits. We perform placement and routing at two levels of design abstraction: microarchitecture and circuit level. Our objective is to optimize performance, power, and size while addressing several important reliability issues such as thermal hot-spot, leakage power, and power-supply noise. The intellectual merit of the research is to conduct the first detailed hierarchical study on how 3D technology impacts the organization of processor microarchitectures and their circuit implementation. First, 3D-aware design decisions as early as in the microarchitectural floorplanning stage are crucial in addressing the opportunities and challenges for using 3D technology. Second, a proper management of the thermal-via, through-the-silicon-via, and decoupling capacitor is a highly effective means of alleviating the ever-worsening thermal, leakage, and power-supply noise problems in 3D integrated circuits. Third, retiming is a powerful tool to reduce both dynamic and leakage power under performance constraints while considering the statistical behavior of the gate and interconnect delay caused by process variations. Finally, we are investigating a number of interesting topology styles for the 3D clock network and demonstrate how to consider clock skew variation under thermal and voltage variations. The broader impact of the research is to call for a very strong collaboration between researchers from the microarchitecture and EDA/physical design areas that will bridge the disciplines to deliver better processor technologies. Similarly, students working on the research are gaining multi-disciplinary and cross-cutting experience from low-level areas such as circuit design, physical design, thermal modeling, and noise modeling, to high-level topics, including microarchitecture design and multi-objective/multi-constraint optimization algorithms.