Collaborative Research: Hierarchical Testing and Yield Enhancement of High End Integrated RF Systems

Georgia Tech Research Corporation, Atlanta GA

Investigators

Abstract

0541005 Milor, Linda Georgia Tech Research Corp Collaborative Research: Hierarchical Testing and Yield Enhancement of High End Integrated RF Systems A wide variety of applications, including home electronics, personal devices, local area networks, bioelectronic monitoring devices, etc., rely on wireless communications. The trend for increased wireless communications forces the use of higher frequency bands (15-60GHz) to avoid interference. Although it is very challenging to design systems that operate in the 15-60GHz frequency range, testing of such systems is even more challenging, as the test equipment must at least achieve equal performance. The result is that the cost of test of RF systems often exceeds 50% of project cost. Even if the cost of testing is absorbed into product cost, two trends require a radically new approach to test. First, an increasing component of system cost and source of system performance loss is associated with packaging. The industry is exploring the use of new packaging methodologies involving multiple bare dies. The use of such packaging methodologies requires manufacturers to guarantee chip performance based on wafer probe tests. Second, progressively shorter product cycles require yield enhancement work based on wafer probe data, so that the process of bringing a prototype to production does not exceed the market window. Unfortunately, testing of RF components at wafer probe is currently not possible, due to the high probe capacitances that prevent high frequency measurements. This project addresses these needs by developing new approaches to design-for-test and design-for-yield-enhancement for RF systems for use at wafer probe. It will provide a framework for both of these tasks that enables improved data collection through on-chip sensing structures and improved loop-back-based system test methods, combined with algorithmic methods to enable fast and accurate fault isolation.