Selective Way Activation of Set-Associativity Caches: Low-Power Design and Test

University Of Cincinnati Main Campus, Cincinnati OH

Investigators

Abstract

Today's society highly depends on portable digital devices such as cell phones, PDAs, laptop computers, MP3 players, digital cameras/camcorders, etc. Battery life is one of the major concerns when using these devices. Caches have accounted for a significant fraction (30-60%) of the overall CPU chip dynamic and leakage energy, and tomorrow's computer systems will use even larger caches which will consume more power. Thus lowering the power-consumption of a cache system is an important research topic. Set-associative caches are commonly used because they incur fewer misses than direct-mapped caches. One the other hand, they typically have slower hit times and higher power consumption, because multiple tag and data banks are probed in parallel. The goal of this project is to examine address affinity and partial comparison information which can be used to reduce operational cache set-associativity, thus save cache access energy and some times even access latency. Two new cache architectures will be studied to significantly reduce the dynamic power consumptions for set-associative caches. Other research topics include new fault models, test methods, and fault-tolerant designs for cache memories that implement low-leakage power dissipation circuits using the drowsy cache technique.