CAREER: Practical Transactional Memory for Highly Parallel Systems

Stanford University, Stanford CA

Investigators

Abstract

With uniprocessor systems running into fundamental limitations such as power consumption and design complexity, single-chip multiprocessors provide a realistic path toward scalable performance for server, embedded, and desktop applications. Nevertheless, the key factor limiting the potential of multiprocessor architectures is the difficulty of developing parallel programs. Existing multithreading models with lock-based synchronization introduce complex tradeoffs between functional correctness and performance that most programmers cannot master. Transactional memory provides an alternative model for concurrency management in multiprocessors based on the well-known database concept of atomic transactions. This project will develop new multiprocessor architectures to efficiently implement transactional memory. The first goal is to define the architectural semantics of transactional memory that support intuitive parallel programming models. The second goal is to develop practical hardware implementations of transactional memory that provide high performance in single-chip multiprocessor systems. The project will result in a restructuring of the hardware and software interfaces for synchronization and concurrency management and will pave the way towards multiprocessors that are easy to program, cost-effective to implement, and fast. The project will also provide students with the knowledge and skills necessary to develop and efficiently program the next generation of single-chip multiprocessors for server, embedded, and desktop applications.