Self-Adjusting Architectures/Circuits for Improved Performance and Reduced Design Complexity

Northwestern University, Evanston IL

Investigators

Abstract

Recent trends of nanoscale integrated circuits will not be mitigated by contemporary architectural innovations and will introduce significant bottlenecks in the design of future microprocessors. First, the growing complexity of models for high performance circuits make it difficult to identify critical characteristics which could aid architects in optimizing the design. Second, there is an increasing variability both in the process parameters and in environmental variables such as power supply and temperature. These increasing variations are directly reflected in microprocessor yield statistics as more manufactured chips fail to meet performance targets. Furthermore, it will be difficult if not impossible to recover from these losses with architectural modifications, which do not directly consider the circuit level causes. Without intervention, the design cycle of future processors will be dominated by exhaustive verification related to model complexity and parameter variation. This project offers a paradigm shift where the design cycle features focused analysis of possible failures and the addition of self-monitoring, self-adjusting mechanisms that can both improve the yield, increase the performance, and reduce the requirements of verification. At the heart of this approach lies the design of flexible architectures that can tolerate variations. Particularly, this project involves generation of: (1) variation-aware architectural models which are based on physical properties and are essential for an initial estimate of the critical segments in the processor and possible failures, as well as tradeoff studies, (2) innovative self-adjusting architectures which consider physical aspects of circuits and can be reconfigured based on in-field readings, (3) algorithms for placement of sensing and monitoring elements on the chip as well as the deployment of the adaptive structures and determination of the adaptation type needed, and (4) circuit synthesis algorithms, which determine how to adjust processors for improved yield and performance. This project directly attacks a critical problem in the microprocessor industry: process variation, and hence would have significant commercial and social benefits. Academic benefits include the close interaction between the design automation, circuits, and architecture researchers and educators. This will open new avenues for learning and present a new set of interesting challenges.