CRI - RAMP: Research Accelerator for Multiple Processors Creating a Parallel HW/SW Platform and Community Vision

University Of California-Berkeley, Berkeley CA

Investigators

Abstract

Abstract Program: NSF 04-588 CISE Computing Research Infrastructure Title: CRI - RAMP: Research Accelerator for Multiple Processors Creating a Parallel HW/SW Platform and Community Vision Proposal: CNS 0551739 PI: Wawrzynek, John Institution: University of California-Berkeley The principal investigators will develop a community resource that enables research on multi-core processors with 64 to 1024 processors on a chip. This will address the problems of research methods for single core processors that do not adapt well to multi-core systems, and go beyond the current empirical methods for small designs with 2-4 processors on a chip. The investigators will utilize field programmable gate arrays (FPGA's), develop boards with multiple FPGA's and systems with multiple boards. In addition to the hardware design, associated software, and register-transfer level models will be developed. The resulting system, RAMP, will be prototyped and provided to several university partners. The system is expected to stimulate advances many computer science areas including operating systems, compilers, debuggers, programming languages, and scientific applications support.