Improved Placement Approach by Incorporating Global Routing and Interconnect Optimization

Iowa State University, Ames IA

Investigators

Abstract

0540998 CHU, CHONG-NUEN Iowa State University Improved Placement Approach by Incorporating Global Routing and Interconnect Optimization As feature size in integrated circuits (ICs) continues to reduce, transistor devices are smaller in size and hence faster in switching. On the other hand, interconnect wires become narrower, and hence more resistive and slower in transmitting signals. Since the advent of 250nm technology at 1997, the signal transmission delay caused by interconnect wires has dominated the total delay. With the feature size down to 65nm in advanced ICs, interconnect delay is clearly one of the most important concerns in today's IC design. For a given technology, the delay of an interconnect is mainly determined by its length. In other words, the delay of an interconnect wire can be reduced by placing the two connected transistors closer to each other on the chip. Hence, because of the increasing dominance of interconnect delay in nanometer regime, placement of transistor devices on a chip has become a critical step in the IC design flow. However, in existing placement approaches, the interconnect characteristics are approximated by very inaccurate models. After placement of devices, actual implementation of interconnects is carried out by performing routing (which means the actual layout of the interconnect wires on the chip) and interconnect optimization (which typcially includes widening of wires, changing of driver sizes, and insertion of buffers). Those inaccurate models do not capture these actual implementation details. As a result, the interconnect and device resources required by the routing and interconnect optimization steps are not adequately estimated and reserved during placement. Thus, the placed circuit may not be routable and the interconnects may not be successfully optimized. In that case, the circuit must be placed, routed and optimized repeatedly until routing can be completed and the performance after interconnect optimization is satisfactory. Such an iterative process may take a long time to converge or may not even converge at all. Even if a routable circuit is finally obtained, the quality of the placement solution is inevitably poor because placement is based on rudimentary interconnect information which is very different from that after routing and interconnect optimization. Therefore, there is a critical need for a novel approach to accurately consider the impact of interconnects during placement. The objective of this proposal is to design an efficient approach to incorporate routing and interconnect optimization into placement. Efficient algorithms will be developed to handle the enormous complexity, complicated metrics and restrictive constraints in modern and future industrial designs. Successful development of the proposed approach is essential for future large-scale designs in the nanometer regime to achieve superior performance and short time-to-market previously not possible.