CAREER: System-level Design of Network-on-Chip Architectures

Arizona State University, Scottsdale AZ

Investigators

Abstract

0546462 PI: Karamvir S. Chatha Arizona State University CAREER: System-level Design of Network-on-Chip Architectures System-on-Chip (SoC) architectures in future will be implemented in less than 50nm technology and include tens to hundreds of heterogeneous processing element blocks operating in the multi-GHz range. The on-chip interconnection network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection networks or Network-on-Chip (NoC) has emerged as an attractive alternative to traditional bus-based architectures for satisfying the communication requirements of these multi-core SoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addition to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design problem would entail a joint optimization of the thermal profile of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models. The project accomplishes the following three tasks for the IP re-use based methodology for design of NoC architectures: (i) Development of design and optimization techniques for NoC architectures: The techniques support design of NoC architectures with both regular and custom topologies. The design techniques address the issue of thermal floorplanning, high power consumption, and long signal propagation delays that arise in nanoscale technologies. (ii) Development of a customizable IP block for NoC router: The customizable features of the router architecture permit its integration into NoC design flows for both regular and application-specific topologies with multiple levels of quality-of-service. (iii) Development of performance and power consumption models for the customizable router: The models that are at various levels of abstraction enable design space exploration, optimization and performance verification of NoC architectures. The education contributions of the project include development of catalogue of course projects on NoC, recruitment of undergraduate students for graduate school, technology transfer through industry focused curriculum, and increased participation of under-represented groups. Intellectual merit: Multi-core SoC devices are the only solution to the power consumption roadblocks of technology scaling. The project overcomes a key challenge to the successful realization of multi-core SoC devices in deep nanoscale technologies. The project also achieves an appreciable increase in design productivity by enabling the migration of VLSI design to the next higher level of abstraction, namely the system level. Broad impact: SoC architectures that are enabled by the project are the essential component of embedded devices which have permeated through all facets of human activities. Therefore, the project significantly benefits every interface of human-computer interaction including medical instruments, cell phones, automobile controllers, entertainment units, assistive devices and so on. Education impact includes integration of system-level design courses into the undergraduate and graduate curriculum.