Emerging Reliability Issues of Nano-Scale SOI Technology

George Mason University, Fairfax VA

Investigators

Abstract

The objective of this research is the investigation of the following reliability concerns of nano-scale Silicon on Insulator (SOI) chip technology and devices: Hot Carriers (HC), Negative Bias Temperature Instability (NBTI), and Electro-Static Discharge (ESD) protection. The approach will be first to address each of the above reliability concerns individually, and identify the underlying mechanisms in each case. Following this, their interdependence and interaction will be addressed on account of the fact that the responsible mechanisms are usually active simultaneously. The investigations will be primarily experimental, on samples supplied by leading semiconductor manufactures, but substantial numerical simulations will also be done as/when needed. Two Ph.D. students will work under this proposal, and the research group will remain focused and informed through student summer internships and frequent discussions with leading semiconductor industry collaborators. The expected impact of this research derives from the realization that when SOI devices are shrunk at the nano-level, they operate at elevated temperatures and the underlying degradation mechanisms behave in complicated ways; and the expectation that SOI will play a major role in future silicon chip technology nodes. This research will help identify the best designs for optimal reliability and performance. The educational environment will be impacted and enhanced by having several undergraduates (including underrepresented groups) "join the team" and work on their senior design projects. Further, the group will mentor the teaching assistants for the microelectronics courses and provide support to set-up and update experiments, prepare manuals, and maintain the necessary simulation tools and design software.