CSR--AES: Multiprocessor Chip for Modular Software

Massachusetts Institute Of Technology, Cambridge MA

Investigators

Abstract

The project will design and evaluate a novel architecture and programming model for a general purpose multiprocessor chip. The chip will include eight to sixteen processors, each of which is of simultaneous multithread organization and capable of superscalar performance. The memory model will support a 64-bit address space of 1024-bit "chunks" of memory used to hold programs and data shared by all users. Active chunks will be held in on-chip fully associative cache units, and ''paged'' to off-chip memory when replaced by newly active chunks. A unique feature of this proposal is that chunks of data are created, initialized, accessed, and released, but are never updated. The result is a system in which there is no cache consistency issue, implementing security of memory access is straightforward, and memory management is readily implemented in hardware. Application programming will be supported in the Java programming language, restricted so that the Secure Arguments principle for modular software components is satisfied, and implicit parallelism can be the basis for achieving high levels of parallel processing performance. The work to be performed includes implementing a cycle-accurate simulation of the proposed multiprocessor chip, developing a translator from Java bytecode class files to the proposed multithread instruction set, and evaluating programmability and performance for several representative applications.