NANO: The Fundamental Science of Ultra-High Density Logic Circuitry

California Institute Of Technology, Pasadena CA

Investigators

Abstract

Project Summary In 2004,the 90 nm node for CMOS-based Si integrated circuits was commercialized.90 nm refers to the 'half-pitch ' between the most closely spaced metal lines the actual pitch of those lines is 180 nm..Assuming that the current scaling trends continue,technology nodes within the 10-15 nm range would be commercialized around the timeframe 2020 or so.It has previously not been possible to even explore circuitry at these dimensions,since no patterning method for creating such ultra-high density semiconductor circuitry existed.However,the SNAP (superlattice nanowire pattern transfer)method has been recently demonstrated as capable of producing relatively large scale,highly conducting Si nanowire circuits at these dimensions. The work proposed herewill utilize these circuits,and will focus on addressing some of the most fundamental,chemical,and materials issues that are associated with scaling semiconductor computational circuitry to near molecular dimensions.The intellectual merit of this work will be to establish whether or not it is even possible to scale CMOS circuitry to such extremes.The broader impact is that,regardless of what computational paradigm follows the current one,a high levelof manufacturing perfection at the atomic scale is likely to be necessary. The work described in this proposal will lay much of the foundation for achieving such perfection. In the spirit of the RFA,certain approaches described here require manufacturing at a near atomic level of control,although parallel fabrication approaches for achieving such perfection are proposed,rather than atom by atom assembly approaches.Also,in the spirit of the RFA,architectural approaches for novel omputational schemes,such as those that can take advantage of highly regular circuit structures,or that can bridge length scales from the nano-scale of the logic circuits to the sub-micron scale of standard lithography,will be exploited. In fabricating and utilizing ultra-dense silicon circuitry,several chemical and materials issues become im- portant.For example, as Si wire widths are reduced to a few nm,the role that surface states play in the conductivity characteristics of the nanowires becomes increasingly important.Since oxide passivation of Si reduces the mobility of charge carriers near the surface,we want to replace the oxide with an atomically perfect (and very thin)surface passivant.We propose to explore the use of methyl termination of Si(111)for applications to these circuits,an alternative that has been demonstrated to be air-stable with atomically complete passivation that dramatically reduces the surface charge carrier recombination velocities. Silicon conductors with a thin,high-k gate dielectrics and metal gate electrodes are envisioned to become important by decade 's end.Equally important for more extreme scaling,will be low-k dielectrics that serve to electronically isolate one nanowire from its nearest neighbor,so that the field-gating can be localized to individual nanowires within a high density logic circuit.These issues will be addressed by combining theoretical modeling to determine effective dielectric constants of ultra-thin materials and molecular films with experimental studies incorporating atomic-layer deposition of high-k gate dielectrics (i.e.HfO2)coupled with the incorporating low-k dielectrics for separating the Si nanowire conductors. Finally,ultra-high density patterning methods will likely be limited in terms of the physical complexity achievable in a circuit design.This requires the incorporation of novel approaches for bridging the length scales between the sub-micron world of lithography and the nanometer world of ultra-high density circuits.It also requires novel architectural concepts to take advantage of highly-or quasi-regular patterning methods.Architectural approaches that solve these issues will provide a driver for much of the fundamental science described herein.