CAREER: Variational Methods for Design Complexity in Nanometer VLSI Circuit

University Of Arizona, Tucson AZ

Investigators

Abstract

0447900 Janet Wang University of Arizona CAREER: Variational Methods for Design Complexity in Nanometer VLSI Circuit The growing design complexity of nanometer scale (component length ~ 10-9 m) VLSI/ULSI (Very- and Ultra-Large-System-Integration) circuits cause escalating research/design costs that are likely to hinder the creation of cheaper and faster computer processors. To illustrate, the current Complementary-Metal-Oxide-Semiconductors (CMOS) processes requires complicated physical modeling in order to accurately predict the performance of the fabricated product. Process variation, coupling capacitance, mutual inductance, and MOSFET leakage currents are jargon-specific concepts for such intricate physical details peculiar to components (e.g. gates) of very small (~ 10-9 m) physical dimensions. These time-variant, unsteady effects induce severe uncertainties < /B>in the operating speed of the cicuit, in the integrity of the pre- and post-circuit signal, in the power consumption, and in the distribution of undesirable hot-spots within the circuit architecture. The PI strives to alleviate design cost through the creation of Electronics Design Automation (EDA) tools that benefit from specialized variational analysis techniques. As the acronym implies, EDA tools automate many steps of the circuit design and reduce the complexity workload for the design engineer. Thi s CAREER proposal outlines a hybrid research/education program for The University of Arizona at Tucson. The research program is expected to generate indispensable and applicable knowledge in modeling , design, and verification of increasingly complex ULSI circuits whereas the educational component endeavors to train students in the creation, upgrade, and maintenancy of future EDA tools. The following technological broader impacts are likely to manifest themselves through the proposed research. An improved ratio of functional to defective units in a microprocessor batch (yield production) would translate into immense revenue savings for high volume manufactures. Chip circuit designers may have the option to adjust important design parameters (e.g. chip clock frequency) to maximize the performance of the processor. The ability to predict full chip/package temperature profile would allow the elim ination of hot-spots that negatively affect the performance of the circuit. Advanced EDA tools would automate complex design rules and streamline the design decision process for upcoming new bio- and nano- materials. The increased availability of under- and post-graduate cutting-edge electronics eduction for women and minority constitutes an important social broader impact that provides these sectors with skills to compete in the high-end Integrated Circuit (IC) design industry within the next 20 years.