Exploiting Fast On-Chip Wires

University Of Utah, Salt Lake City UT

Investigators

Abstract

Exploiting Fast On-Chip Wires Abstract As VLSI technology scales below 100 nanometer feature sizes, the performance of chip-based systems will be limited by the cost and delay associated with on-chip communication. An important problem facing future microprocessor designers is the efficient movement of data on a chip. The objective of the proposed research is to accurately characterize the cost and performance options for on-chip interconnect, and to develop micro-architectural approaches that use these options efficiently. The expected result is a novel class of hybrid architectures that utilize a small percentage of their wire budget on costly, low-latency long wires to achieve enhanced performance/cost.