Achieving High-Performance Reconfigurable Computing in Commodity Devices

University Of Washington, Seattle WA

Investigators

Abstract

Achieving High-Performance Reconfigurable Computing in Commodity Devices Abstract FPGAs are chips that can be programmed and reprogrammed to implement complex digital logic. They combine the performance of hardware with the flexibility of software. Potential applications range from hardware accelerators for high-performance computers, as well as in everyday electronic devices. Thus, improving their performance is of significant interest. Although FPGAs can provide high performance for a wide range of applications, their achieved clock cycles are typically 5x-10x slower than other circuits. This is due to the programmable nature of the underlying hardware, as well as the limitations in the input circuits. FPGAs can support much higher theoretical clock rates than currently can be achieved in practice. This research will develop architectural features and tools needed to realize this potential. This approach will combine established techniques with new algorithms for generating and mapping highly pipelined circuits. The key is to allow for very significant levels of circuit pipelining in situations that demand it, while trading area for performance. We will also optimize the FPGA architectures to support pipelining, while not adversely affecting general-purpose designs. This will include optimized logic blocks that can support aggressive pipelining, as well as routing designed for interconnect pipelining. This proposal contains new approaches to radically increase the speed of FPGAs, a major building block in today's electronics systems. By providing faster hardware, we can provide greater flexibility, capabilities, and speed in many different systems. This may include high-end computers with reconfigurable hardware units, and versatile electronics like multi-network, multi-service cell phones and enhanced multi-media capable PDAs.