ITR - (ASE) - (int): CAD for Reducing Soft Error Failure Rates in Logic Circuits

University Of Texas At Austin, Austin TX

Investigators

Abstract

Proposal ID: 0426608 P I: Touba, Nur Organization: University of Texas at Austin Title: ITR - (ASE) - (int): CAD for Reducing Soft Error Failure Rates in Logic Circuits Abstract: Reducing the soft error failure rate for logic circuits is more expensive and difficult than for memories and is expected to emerge as a very important problem in the future for mainstream low-cost electronics as technology continues to scale. Currently, there is a lack of computer-aided design (CAD) tools and techniques for addressing this problem in a cost-effective manner. This research project involves developing a new paradigm for designing logic circuits with protection from soft errors to reduce the soft error failure rate. A fine-grain quantitative approach will be investigated where the susceptibility of the logic circuit to soft errors is estimated at each step of the design process and fault tolerance features are incorporated as needed in a cost effective way to satisfy soft error failure rate requirements. One of the key ideas in this research is to exploit the asymmetric soft error susceptibility of internal nodes in a logic circuit to direct the insertion of fault tolerance features. Unlike memories where the probability of a soft error in each cell is equally likely, in logic circuits upsets at some internal nodes can have orders of magnitude greater probability of being latched and causing a soft error than at other nodes. By focusing error detection and/or error masking capability towards the nodes that are most susceptible to soft errors, the soft error failure rate in logic circuits can be significantly reduced at a fraction of the cost of existing techniques which try to guarantee coverage of all nodes. The objectives of this project include developing efficient procedures for estimating soft error susceptibility, developing CAD algorithms for cost-effective insertion of fault tolerance features, and developing soft error protection schemes that minimize impact on timing and power.