NER: Exploring Nanodevices for Probabilistic Computing Architectures

Brown University, Providence RI

Investigators

Abstract

PROPOSAL NO: 0403958 INSTITUTION: Brown University PRINCIPAL INVESTIGATOR: Zaslavsky , Alexander TITLE: NER: Exploring Nanodevices for Probabilistic Computing Architectures Abstract: The progress of modern transistor-based digital technology has depended on shrinking silicon transistor to ever smaller sizes and integrating more of these transistors into logic circuits. At some point in the next decade, however, transistors will reach their ultimate physical size and circuits will contain so many transistors that some nonworking devices are inevitable. As a result, we may need both new types of devices to replace silicon transistors or new types of logic architectures that can tolerate some number of defective devices in a circuit, or both. The proposed exploratory research targets both of these issues. We propose to map our previously developed probabilistic computer architectures onto real experimental devices, that will be fabricated from carbon nanotube material. Conversely, the nonlinear characteristics of the nanotube device prototypes will provide the experimental inputs to designing more advanced fault-tolerant logic circuits.