U.S.-Japan Cooperative Science: Efficient Test and Diagnosis Techniques for System-on-Chip

Duke University, Durham NC

Investigators

Abstract

0403217 Chakrabarty This award supports a two-year collaborative research project between Professor Krishnendu Chakrabarty at Duke University in North Carolina and Professor Seji Kajihara at Kyushu University in Japan. They will be undertaking research on efficient test and diagnosis techniques for system-on-chip (SOC). Recent advances in VLSI technology have lead to a rapid increase in the density of integrated circuits (ICs). The increased density and the need to test for new types of defects in nanometer technologies result in a tremendous increase in test data volume. The increase in test data volume not only leads to the increase of testing time, but the high test data volume may also exceed the limited memory depth of automatic test equipment (ATE). Multiple ATE reloads are time-consuming since data transfer from a workstation to the ATE hard disk or from the ATE hard disk to ATE channels is very slow. The researchers will investigate several new approaches to reduce test data volume and testing for ICs. These techniques are based on data compression methods, alternative scan architectures, and built-in self-test (BIST). Compression techniques from the image-processing domain, such as quad tree decomposition, will be explored. A scan design approach will be developed in which a small number of ATE channels will be used to drive multiple scan chains. Finally, new linear-feedback shift-register (LFSR) reseeding architectures will be developed in which the seeds for the LFSR can be shifted into the LFSR through a designated flip-flop, which can be selected from a set of predetermined flip-flops of the LFSR. ICs are widely used in today's electronic systems, with applications ranging from microprocessors and consumer electronics to safety-critical systems such as medical and aircraft control systems. In order to ensure the reliable operation of these systems, high quality testing of ICs is essential. To reduce product cost, it is also necessary to reduce the cost of testing without compromising product quality in any way. This project is expected to lead to low-cost test techniques for ICs, ranging from external testing using data compression to BIST solutions. This research will eventually allow even higher levels of integration in SOC designs, and help bridge the gap between design capability and manufacturing capacity. The broad impact of this research will be seen in reduced design time and enhanced reliability of a wide range of electronic products. The project brings together the efforts of two laboratories that have complementary expertise and research capabilities. Through the exchange of ideas and technology, this project will broaden our base of basic knowledge and promote international understanding and cooperation. The project includes the participation of a graduate student. Results of the research will be disseminated at scientific meetings and in scientific journals.