CAREER: Intelligently Managing the Memory Hierarchy of Future High Performance Servers

North Carolina State University, Raleigh NC

Investigators

Abstract

CAREER: Intelligently Managing the Memory Hierarchy of Future High-Performance Servers Abstract The research addresses the unique challenges facing high-performance server design in the billion-transistor chip era. Chip multiprocessors consisting of multiple cores that share the memory hierarchy and run many independent threads simultaneously, represent one direction for future parallel architectures. In such architectures, the contention for shared resources such as caches and off-chip bandwidth can produce thrashing and degrade the server performance significantly if not properly managed. In this research a synergistic approach involving computer architecture, compiler, and operating systems is advocated to tackle the problem of resource management in chip multiprocessor based servers. An intelligent memory hierarchy is proposed (i) to provide fine-grain inter-thread management of resources like caches, off-chip bandwidth, and main memory (ii) to offload critical memory-bound functions from the server and (iii) to reduce context switch overheads.