CAREER: Microarchitecture Considerations for Soft-Error Tolerance in Future Microprocessors

Carnegie Mellon University, Pittsburgh PA

Investigators

Abstract

CAREER: Microarchitecture Considerations for Soft-Error Tolerance in Future Microprocessors Abstract This project addresses the pressing issue of increasing susceptibility to soft errors in future deep-submicron microprocessor implementations. The study develops and evaluates three candidate approaches for detecting and recovering from soft errors. The three approaches are dynamic instruction re-executions in a superscalar processor, redundant executions over two mirrored processor cores facilitated by an efficient crosschecking mechanism, and an all-software approach for unmodified simultaneous multithreading (SMT) processors or chip-multiprocessors (CMP). The study evaluates the potential of each approach and analyzes their trade-off in terms of performance, fault coverage, design complexity and implementation cost. A goal of this research is to overcome the performance and implementation penalties associated with these approaches. An education component of this project applies executable and synthesizable high-level hardware description formalisms to improve the preciseness of in-class discussions and to enable more insightful out-of-class independent exercises. Following decades of exclusive focus on performance, soft-error reliability is one of the key challenges in the continuing advances of microprocessor designs. The results of this research have direct bearing on the multi-billion-dollar microprocessor industry, which in turn will impact our daily experiences from professional to recreational. The results of this research will not only be applicable in the near term to deep-submicron VLSI microprocessors, but may also be extensible to address the reliability of emerging technologies such as quantum, molecular and nano-technologies.