CAREER: Designing with Light: Comparative Analysis and Design of Optical Interconnects for Chip-to-Chip Communication

Cornell University, Ithaca NY

Investigators

Abstract

PROPOSAL NO: 0347649 INSTITUTION: Cornell University-Endowed PRINCIPAL INVESTIGATOR: Apsel, Alyssa TITLE: Designing with Light: Comparative Analysis and Design of Optical Interconnects for Chip-to-Chip Communication Abstract: CMOS electronics have become ubiquitous in modern society, continuing to create both technological and economic opportunities in such areas as portable computing and handheld devices. In the past, the capabilities of CMOS processors have been limited internally by transistor density, power consumption, and speed. All of these characteristics have improved consistently with transistor scaling, governed empirically by Moore's Law. However, as CMOS feature sizes decrease into the sub-micron regime, electrical signaling and interconnect problems promise to become the ultimate limit of high performance systems at both the board and chip levels. Integration of optical interconnects into high-performance computing offers a promising and necessary approach to solving the inter-chip communication bottleneck. The goal of this project is to provide a framework for design of short distance chip-to-chip optical interconnects that addresses the unique problems and requirements of these microelectronic systems. Through research in the field of chip-to-chip optical interconnect design, I have found that existing models for optical interconnects in large scale networks fail when applied to small chip-scale networks. By performing analysis tailored to smaller chip scales and integrating these new approaches with usable modeling tools, we will enable optical interconnects to be added into the design catalog of mainstream CMOS designers. In order to achieve this we propose a two-pronged research plan composed of both investigation and development of feasible high speed interconnects. A goal of the first part of the proposed research is to develop a methodology for interconnect optimization by performing a comparative analysis and testing of various interconnect architectures, as they would be applied in a multi-chip module (MCM). In the second segment of this project, we will develop the framework for CAD supportable models of short distance optical interconnects, standard CMOS cell libraries for optical interconnect, and a set of simple design rules applicable to optimized short distance interconnect design. The results of this work with be both a better understanding of use of hybrid technologies to solve scaling problems in CMOS systems as well as a demonstrated physical means of carrying out this type of design within a computational CMOS architecture. The educational aspect of this project focuses on integrating research into teaching and other educational activities at the high school, undergraduate, and graduate levels. A crucial step in removing barriers to innovation by students and future designers is to educate them in hands-on interdisciplinary research and allow them to develop and test novel design methodologies. In following with this idea, a third goal of this work is to engage students at all levels by providing them with "hands on" design experiences and exposure to research that develops both critical thinking and laboratory skills. This project provides many opportunities for students of VLSI design to practice hands on learning and develop critical thinking skills both in the laboratory and in the classroom environments.