SGER: Novel Phonon Engineering Concepts for Nanoscale Devices and 3D Integrated Circuits

University Of California-Riverside, Riverside CA

Investigators

Abstract

The problem of heat removal becomes crucial for continuing CMOS downscaling, beyond CMOS nanoscale concepts, ULSI, and 3D architecture proposals. Conventional heat removal methods and post device-design / packaging level cooling solutions fail to work at nanoscale and in 3D architectures. This proposal introduces a drastic philosophy change in heat removal, e.g. thermal management features incorporated at the materials / device level, as well as two new radical concepts of heat removal via phonon engineering such as (i) thermal conductivity enhancement of the material along chosen directions via proper engineering of device heterostructures and (ii) smart arrangement of the nanoscale devices in ULSI circuits or in 3D architectures to achieve acoustic phonon interference and phonon annihilation, e.g. local cooling, in pre-determined locations.