ITR: Architectures and Design Methodologies for Secure Low-Power Embedded Systems

Princeton University, Princeton NJ

Investigators

Abstract

Embedded systems, for example in information appliances and networked sensors, face some of the most demanding security concerns - they are resource constrained while frequently needing to handle sensitive information in physically insecure environments. Security processing can easily overwhelm the limited computation and memory resources of embedded processors, especially with the escalation in the amount of data to be processed and the data rates of high-speed networks. This "performance gap" is compounded by the "battery gap", which is the disparity between energy requirements and slow improvements in battery technology, for secure low-power embedded systems. This project is an inter-disciplinary study of several core technologies that will enable the design of secure, low-power embedded systems. It spans the fields of security, cryptographic algorithms, embedded processor architecture, computer arithmetic, low power design, and enabling design methodologies and tools. It addresses the performance, energy and security requirements, and their tradeoffs, in embedded processors and systems. The research goals include a comprehensive analysis of the performance requirements and power consumption for security in embedded systems. The project is developing efficient architectures for security processing in low-power embedded systems, including configurable security modules for system-on-chip designs, and architectural guidelines for tiny cryptographic processors for embedded systems. The performance, power and security tradeoffs based on customizations at the protocol, cryptographic algorithm, and hardware and software implementation levels are studied. Design methodology and tools include processor design tools to facilitate the design of new security processing architectures based on open frameworks such as the PLX (hosted at Princeton) and SimpleScalar toolkits. The project explores domain-specific design methodologies that jointly co-design security protocols and processing architectures to meet the required security, performance and power priorities and constraints. The research enables the design of embedded systems with higher levels of security, while achieving an order of magnitude or more in performance and battery life, compared to conventional approaches. Broad security impacts are expected for embedded system design, in addition to impact for future research and education. Results are disseminated to industry through the Princeton Architecture Lab for Multimedia and Security (PALMS) and the NJCST Center for Embedded System-on-a-Chip Design. The research results are being woven into graduate and undergraduate courses.