ITR WaveScalar: A New Approach to Scalable System Design

University Of Washington, Seattle WA

Investigators

Abstract

Wavescalar, A New Approach to Scalable System Design Abstract At the center of our modern society is the rapid growth and pervasiveness of Information Technology (IT). This has been made possible by the exponential increase in raw silicon fabrication capabilities enabling a rapid increase in computational power. Recent research has shown that scaling up our current microprocessor models will no longer convert these advances in technology to commensurate increases in performance. WaveScalar is a new processor architecture designed to scale into the next decade and beyond. It is designed to directly confront the emerging problems of wire delay by transforming the large slow broadcast networks of a superscalar into short fast point-to-point links. It is constructed from a grid of simple-to-design uniform processing nodes whose complexity is three orders of magnitude less than current processor designs. The research undertaken from this proposal will tie together the architecture, compiler, and operating system foundations of this new microprocessor model. The architecture research includes a detailed design of the architecture of the WaveScalar system, including investigation of node design, instruction placement, and system interconnects. The compiler research includes developing new optimization techniques specific to WaveScalar and assisting the microarchitecture through compiler support. The operating system component includes a study of basic primitives of operating systems in this new computing platform including mechanisms for application specific memory management and context switching. Finally, WaveScalar is a low-complexity, highly threaded architecture and as such may be well suited for nanotechnologies. A detailed investigation of the WaveScalar architecture for these emerging technologies will be undertaken.