ITR/NGS: Toward Autonomous Computing Platforms: System-Wide Hardware/Software Performance Monitoring and Adaptation

Cornell University, Ithaca NY

Investigators

Abstract

The proposed research will develop a flexible and unifying framework for non-intrusive hardware monitoring of virtually any system component, to enable methods and tools to build systems that can be autonomous, self-aware, self-adapting, and self-healing. Building such systems requires the existence of flexible, introspective data acquisition mechanisms to determine the state of the system, to detect alfunctions or inefficiencies, and to provide the basis for appropriate adaptation (to steer system configuration and optimization). Whereas current systems provide only limited access to specific events (prohibiting system-wide event correlation and global state evaluation), we will provide: o System-wide, unified introspection as a building block for autonomic systems; o Data preprocessing on the actual monitoring probes (by leveraging reconfigurability); o Standardized access to performance information using high-level queries; o Integration of hardware and system software probes in a common framework; o Correlation of performance information from several sources to assemble global system state for requested metrics; o Autonomic optimization of system components, including the Operating System (OS), runtime, and compiler; o Ability to optimize for performance, power savings, heat dissipation, security, and reliability, all within a single framework; The intellectual merit of the proposed work includes a) laying the architectural and system software foundations for introspective systems, b) developing and testing a design for non-intrusive, flexible hardware monitoring of system behavior, and c) demonstrating the effectiveness of our approach and design in three main ways. We will dynamically optimize interconnect performance for a DSM cluster; deploy plug-and-play monitoring modules for the K42 multiprocessor OS, and perform dynamic system reconfiguration based on the information gathered by these modules; and demonstrate via simulation the opportunities for dynamic adaptation within the processor core and memory hierarchy. The broader impact of this work includes distribution of our tools and infrastructure to the research community.