ITR: Synchroscalar: Exploiting Synchronized Clock Domains for Energy Efficient Multirate Embedded Computation

University Of California-Davis, Davis CA

Investigators

Abstract

Chong ITR: Synchroscalar, Exploiting Synchronized Clock Domains for Energy Efficient Multirate Embedded Systems Abstract Ubiquitous computation and communication devices will dominate the social and economic landscape of the new millennium. As the functionality of these devices evolve, current microprocessor designs cannot keep up with the battery life and the performance requirements. We propose to address this problem with a novel microprocessor design that uses a combination of two approaches. First, we break the work into many parallel pieces to increase performance. Second, to save power, we run each piece at the minimal speed necessary to achieve the quality of communication desired. Specifically, we propose the Synchroscalar architecture, a two-dimensional mesh of processing tiles in which each column forms a separate clock and voltage domain. Clock frequencies are related by a rational factor, which will be exploited to schedule data transfers between different clock domains without incurring the overhead of asynchronous communication between clock boundaries, yet retaining the benefits of optimal clocking for each column. This organization gives us the many of the energy advantages of asynchronous systems while maintaining the simplicity of a synchronous system. The success of these approaches will significantly increase the impact of information technology on the nation, enabling many "wired" applications to become wireless and mobile.