SGER: Evaluating Reliability of Defect Tolerant Architectures for Nanotechnology using Probabilistic Model Checking

Virginia Polytechnic Institute And State University, Blacksburg VA

Investigators

Abstract

With the advances in silicon technology as predicted by Moore's law, we are already in deep sub-micron era of device feature size. Currently 90 nanometer (90 nm) is a reality, and very soon we will be in the tens of microns. The technology will then change drastically, with single electron transistors and such artifacts of nano-technology era. As a result, uncertainties about the device behaviors will be a common problem that engineers will have to deal with, in such miniscule quantum level of technology. Currently, while designing computer architecture components, engineers safely assume that the transistors and logic gates will behave as predicted by the theory. However, with uncertainties being rampant in nano-technology, one can only rely on the measures of the probability that a transistor will behave correctly, or a logic gate will function correctly. As a result, in order to implement a logic function and to depend on it with high degree of reliability, engineers will have to build redundancy in the design, such that if some of the gates fail, even then, the functional block will provide the correct functionality with very high degree of reliability. However, how to build redundancy for particular logic functions, and how much redundancy is enough, and at what level of redundancy, the reliability actually decreases, are questions to be answered by an engineering tool, before such redundancy is built into the system. Von Neumann looked at similar problems for logic gates since during his time, logic gates were built with valves which were quite unreliable. Information theorists also look at similar problems in terms of noise tolerance by logic functions. However, no tool exists for such evaluations, nor does a precise engineering methodology exist. This project aims at bringing in the novel technology of probabilistic model checking and create a methodology and tool set for evaluation of reliability for different alternate redundant architectures and compute reliability measures before the design is built to steer the engineers in the right directions. This work will help prepare computer engineers in building reliable functionalities on unreliable nano-substrates, given that material scientists can calibrate nano-materials for probability of failures. This work therefore will have great impact in the future computer engineering and logic design. Also it will help educate future engineers to face the nano era and build reliable computing infrastructures.