SGER: Yield Assurance and Optimization for Clockless Wave Pipeline

Oklahoma State University, Stillwater OK

Investigators

Abstract

This work investigates some theoretical aspects of clockless digital VLSI design with emphasis on methods for assessing and optimizing the confidence level, the so-called yield, of the design. The particular system model under investigation is wave pipeline without any clock-controlled operations, the so-called, clockless asynchronous wave pipeline. This work will specifically address and resolve the following problems: theoretical characterization of clockless-specific delay faults and the fault rate; modeling and analysis of yield; testing algorithms and fault-coverage analysis; and finally fault-tolerance algorithms. This work will ultimately establish a sound and adequate theoretical foundation for development of exploratory, yet practical test/diagnosis/fault-tolerance methods in early design stage of clockless wave pipeline, thereby enabling further research towards development of computer-aided design tools for clockless electronic VLSI systems.