Performance Modeling and Algorithm Design for Reconfigurable System-on-Chip Architectures

University Of Southern California, Los Angeles CA

Investigators

Abstract

Prasanna Performance Modeling and Algorithm Design for Reconfigurable System-on-Chip Architectures Abstract This project will explore algorithmic techniques to optimize application performance on reconfigurable System-on-Chip (RSoC) architectures based on a novel concept of malleable algorithms. Malleable algorithms are architecture-platform aware specification of alternate implementations of a given functionality, and form the basis of a new methodology for performance modeling and algorithm design for RSoC architectures. The proposed research will have the following main thrusts. 1. Domain-specific modeling: hybrid performance modeling using high-level analytic performance models and low-level simulations. 2. Energy-efficient designs with malleable algorithms: design of energy-efficient malleable algorithms for a set of embedded benchmarks and applications. 3. System-level optimization: combinatorial approaches including formulations using interval arithmetic and generalized assignment problem. The proposed effort will lead to the development of highly optimized portable and reusable solutions for implementing embedded applications, and the definition of a new methodology for designing energy-efficient soft-IP cores for hybrid architectures consisting of multiple tightly integrated heterogeneous computing elements. The research will complement ongoing advances in design automation, and bridge the gap between the application developer and RSoC platform architectures.