Integrity Monitoring and Recovery Techniques for Next Generation Submicron Microprocessors

Iowa State University, Ames IA

Investigators

Abstract

Integrity Monitoring and Recovery Techniques for Error-Prone Submicron Microprocessors As advances in VLSI technology reduce circuit dimensions dramatically, processor chips become more vulnerable to soft errors. Thus dependability is becoming an increasingly important quality measure of microprocessors. A transient and/or permanent processor failure could have diverse impacts on our daily lives. The goals of the proposed research are: (1) to characterize soft error behavior on commercial microprocessors through fault injection experiments; (2) to provide a guideline for exploiting soft error susceptibility in integrity checking strategy and predicting the error characteristics from the processor's architecture; and (3) to develop comprehensive micro-architectural solutions. We will investigate individual components of the processor with circuit-level approaches. Subsequently, we will study the area overhead vs. fault coverage trade-off to show the effectiveness of our proposed solutions. We will be developing specific tailored dependability solutions that are independent of technology and based on fault occurrence and error propagation characteristics of a given processor architecture. The techniques are easily adapted to future generations of architectures. Since use of microprocessors and micro controllers is very wide spread and affects every aspect of our lives, improvement in the dependability of such systems would have the widest possible broader impact.