High-Performance Computer Architecture in the Nanoelectronics Era: Overcoming the Reliability Challenge

University Of Texas At Austin, Austin TX

Investigators

Abstract

Jacome High-Performance Computer Architecture in the Nanoelectronics Era: Overcoming the Reliability Challenge Abstract The formidable increase in device densities promised by nanoscale integration will be accompanied by a substantial rise in the numbers of faulty devices. This increase in both hard and soft faults poses a major `reliability challenge,' demanding a rethinking of fundamental microarchitectural techniques and components. Indeed, performance will be inextricably tied to reliability. Thus, it is important to investigate how effective reliability-performance tradeoffs can be realized at the microarchitecture level. The proposal includes research on several novel techniques including: reliability driven speculation, adaptive validation via incremental recomputing of speculated values, and exploiting reliability-aware functional units and self-checking capabilities. In addition the research includes devising novel design methodologies aimed at achieving the necessary reliability for microarchitectural components, and models capturing the scaling of delay versus reliability for concrete component designs. Key quality metrics (performance, reliability and yield) will be evaluated through analysis and simulation. The timeliness, strategic importance and huge potential payoff of advances in nanotechnologies are widely recognized. The ability to engineer these technologies into new products will create tremendous opportunities for economic expansion and improved quality of life. Taking these technologies into production environments requires addressing the reliability challenges identified in this proposal. The outcomes of this project are likely to impact the design of future nanocomputing systems.