Tunable High Dielectric Constant Materials Based Phase Locked Loops

University Of Colorado At Colorado Springs, Colorado Springs CO

Investigators

Abstract

0245132 Kalkur Phase Locked Loops are one of the most important building blocks used in a wide variety circuits in communication systems as well as systems as well as clock recovery circuits. Voltage controlled oscillators (VCOs) are one of the most sensitive components in PLLs. LC (inductance-capacitance) type VCOs are used at high frequencies because of their low phase noise and stable oscillation frequency which is determined by the natural frequency of the LC circuit. The most widely used tunable elements in these oscillators are varactor diodes. As the frequency of operation increases, the capacitance and inductance decreases. The diodes fabricated on silicon substrates have significant parasitic capacitance. This results in reduced variation of total capacitance (including self capacitance of the inductor) with voltage and poor tunability for reverse biased diodes. For forward biased diodes the tunable voltage is limited to a few tenths of a volt and it should not exceed the barrier height of the p-n junction. Since the diodes are fabricated within the silicon substrate, the substrate noise changes its capacitance which results in jitter in the VCO output. Now is the time to investigate if there are other tunable elements that can be integrated in to VLSI technology (CMOS and BiCMOS) with better characteristics than diodes. The PI proposes to use high dielectric constant (K) ferroelectric material capacitors like BST (barium strontium titanium oxide) and the newly discovered BCTZ (barium titanium zirconium oxide) as a tunable element. These elements can be isolated from silicon substrates and therefore have lower parasitics and do not have a significant substrate noise problem. The proposed research involves fabrication of high K based capacitors using BST and BCTZ and optimizing their properties to obtain maximum tunability and figure of merit. He proposes to develop a circuit model for these tunable elements and extract the model parameters by electrical characterization. The VCOs, loop filters, phase frequency detectors (PFD) and buffers will be designed and fabricated using standard CMOS technology through MOSIS. In order to reduce cost, he will attach the high-K tunable elements to CMOS chip by flip-chip technology. These modules will be tested to verify tunability, the jitter of VCOs and characterize the performance of PLLs in terms of jitter versus frequency lock range, lock range versus power supply and lock range versus temperature. Intellectual Merit: Developing a tunable element will require significant research on the fabrication and modeling of their electrical characteristics. The optimization of tunability and figure of merit requires understanding of variation of composition, thickness and grain size in thin high-K thin films with process parameters. The development of circuit model parameters is also complex because the elements of the equivalent circuit are themselves functions of applied voltage and frequency. The integration of these tunable elements with a CMOS circuit and the testing of subsystems at high frequencies are also challenging tasks. Broader Impact: This proposal addresses all of the NSF evaluation criteria relating to broader impacts. Graduate students will be involved in the basic research and under graduate students will be sought to perform senior design projects. The knowledge learned in this project will be imparted to students in their related classes. The research will result in a novel tunable element for present and future VLSI technology. The research results will be published in world wide web, journals and conferences. Preference will be given for the recruitment of minority students.