CAREER: A Framework for Addressing Some Fundamental Challenges in Deeply Scaled CMOS Circuit Design

University Of California-Berkeley, Berkeley CA

Investigators

Abstract

Intellectual Merit Design in power-limited scaling era. This proposal presents a general framework of minimization of power and energy in digital CMOS integrated circuits. This proposal presents a framework for designing digital circuits to either minimize power/energy dissipation for given performance or maximize the performance under power/energy constraints. The problem is defined at the circuit level, but is also expanded to include the device, microarchitecture and system levels. This framework will be used in designing signal processing blocks for communications and storage systems. The particular applications targeted are iterative decoders for turbo and low-density parity check decoding. Broader Impacts The broader impacts of this proposed project are twofold: 1) to widen the education in digital integrated circuits including power, energy, as well as robustness as key determining variables within digital integrated circuit designs and 2) to include these areas within the revised edition of a widely used textbook in Digital Integrated Circuit. My education plans aim at providing a solid analytical background and design intuition for our students in the design of digital circuits and systems.