ITR: Enabling Novel Digital Sequential Circuit Designs through Error Control and Noise Tolerance Techniques

University Of Illinois At Urbana-Champaign, Urbana IL

Investigators

Abstract

The proposed research aims at extending the benefits of scaling (i.e., Moore's Law) into the ub-0.07$\mu$m regime by developing error control techniques for digital sequential circuits. The overall goal is to evaluate the practical implications of recently developed dynamic error correction and algorithmic noise tolerance techniques in terms of enabling the design of sequential circuit architectures that are cost-effective and operate at speed and energy efficiencies that exceed the limits imposed by current VLSI architectures. The successful completion of this project can lead to the development of acomprehensive set of circuit design techniques that permit tradeoffs between reliability, speed and energy-efficiency in ways that have not been exploited before. The objectives of this research thrust are two-fold: (i) The immediate goal is to develop error control methodologies that enable the construction of functional sequential systems out of unreliable components that may be fast, inexpensive or have reduced energy requirements. The novelty of the proposed research lies in that it it explores the case when the error correction mechanism operates at a different time scale than the rest of the system. (ii) The ultimate goal is to build prototypes of such sequential circuits in order to evaluate their actual performance and potential. The proposed research also has a significant educational and outreach component, motivating graduate students to contribute to research that focuses on the fringes of circuit theory, signal processing, coding and graph theory, control theory and information theory.