ITR: A Completely Integrated Processor-Memory-Interconnect Architecture for Data Intensive Applications

University Of Southern California, Los Angeles CA

Investigators

Abstract

A new, completely-integrated processor-memory-interconnect (CI-PMI) architecture model suitable for a range of data-intensive applications is proposed. Compared to the existing processor-in-memory (PIM) architectures, the proposed CI-PMI approach integrates more completely the processing, memory, and interconnect. This is achieved by starting with the classical architecture of high capacity memory, namely, a binary tree of decoders with memory modules as leaves, laid out as an H-tree. In the proposed model, copies of one or more types of application-specific computing elements are added at different levels of the memory decoder tree, desired functionality added to the memory decoders to augment their role as interconnects as well as to support desired computation, and, if necessary, additional interconnects added between the application-specific processors, the memory modules, and the decoders. The proposed architecture will be developed and demonstrated for a data-intensive application, namely motion estimation for MPEG encoding. The results of the proposed research will be used to augment one advanced class, to be taught at USC as well as UCI. The class will take a top-down view of advanced processor-in-memory architectures including those developed in this project. The proposed research will advance the state of the art in computer architecture, VLSI, and VLSI CAD, leading to faster and cheaper designs for day to day computation and information retrieval, exchange, and management.