Compiling for Explicitly Parallel Adaptable Architectures

University Of Washington, Seattle WA

Investigators

Abstract

As the demands on portable embedded systems increase with the incorporation of high-bandwidth wireless data along with multimedia and speech processing, it is becoming increasingly difficult to achieve the required performance and power requirements with programmable solutions. Current platforms for high-end embedded systems typically comprise one or more RISC or DSP processors, along with an increasing number of application-specific (ASIC) components that are necessary to deliver high performance at low power. As more and more functionality is implemented using ASIC components, the platform's range of application decreases and its vulnerability to obsolescence increases. Coarse-grained adaptable architectures bridge the gap between traditional processors and ASIC solutions and can be used to replace many of the ASIC components in high-performance embedded platforms. The goal of this research is to make these adaptable architectures accessible to programmers via a high-level programming language interface. This project will develop a compiler comprising a standard front-end combined with a parallelizing backend that performs scheduling and optimization using a simultaneous place and route algorithm based on those used in physical design automation. Posing the scheduling problem as a place and route problem allows the many constraints imposed by adaptable architectures to be solved by a single phase of the compiler.