ITR: Prototyping Multithreaded Systems

Stanford University, Stanford CA

Investigators

Abstract

The goal of the proposed research is to develop a multithreaded prototyping environment that allows hardware and software experimentation with fine-grain and speculative multithread chip multiprocessor (CMP) architectures. This environment will allow the analysis of single-chip fine-grain threaded systems at full hardware speeds in a much more flexible manner than is possible today with software simulation, and will be the first hardware implementation to execute speculatively multithreaded applications. This environment would be used to investigate threaded applications much more efficiently and thoroughly than any other system existing today. The prototyping environment will be built without doing any VLSI design. The key idea is that by combining ten-year-old microprocessor chips with state-of-the-art FPGA chips it is possible to build a single-board multiprocessor prototyping environment that provides support for thread level speculation (TLS) and operates at hardware speeds, yet has the latency and bandwidth characteristics equivalent to a modern CMP architecture. Such an environment will be ideal for architecture and software research on multithreaded microprocessors