ITR: Network-Oriented Memory Hierarchies for Internet Servers

Regents Of The University Of Michigan - Ann Arbor, Ann Arbor MI

Investigators

Abstract

Main memory has long been the weak link in high-performance Internet-connected computer systems, sandwiched between continuing rapid increases in both network bandwidths and CPU performance. As networks reach 10 Gb/s and CPU clock rates shoot past 2 GHz, the memory system is under more pressure than ever to keep up. Meanwhile, increased transistor counts are enabling integration of multi-megabyte caches and DRAM controllers directly on the processor device, with switched interconnects built from high-speed point-to-point channels carrying I/O and memory coherence traffic between chips. This inflection point in the configuration, level of integration, and capacity of the memory hierarchy represents an opportunity to optimize the memory system for high-bandwidth Internet networking support. This research will (1) establish a baseline analysis to characterize the key bottlenecks of future memory hierarchies on Internet server workloads, and (2) evaluate specific system enhancements to address these bottlenecks, leading to more efficient, higher performance Internet server systems.