ITR: Virtual Power for a Wireless Campus - A Vision of Ubiquitous Computing On Low-Cost Mobile Devices

University Of California-Irvine, Irvine CA

Investigators

Abstract

While handheld, battery-powered devices such as personal digital assistants (PDA's) and web-enabled mobile phones are emerging as new access points to the world's digital infrastructure, their cost and short battery life are factors that are holding back their enormous potential. Worse yet, the cost of such devices might even widen the "digital divide". This research addresses these cost and battery-life issues simultaneously, thereby getting one step closer to a vision of ubiquitous computing embracing all of society. The specific focus is the digital university campus with wireless Internet coverage. In this setting, the aim is to increase the utility and battery-life and decrease the cost of handheld wireless computers by enabling the use of relatively simple hardware for the mobile devices. This research aims both at designing embedded hardware that better conserves resources, as well as creating a software layer that masks the limited computational prowess of a handheld device by seamlessly coupling it to a relatively high-powered stationary computational infrastructure via an "always on" wireless connection. By off-loading power-intensive operations to the stationary infrastructure, the battery-powered mobile device is provided with "virtual power". Adaptive just-in-time compiler technology will be developed for minimizing power use on mobile devices running mobile code, and adaptive scheduling methods using results from the Computational Grid research community. Depending on the algorithm to be run on the mobile device and its current distance from the nearest base station, the computation to be performed is to be automatically partitioned between a part to be executed in the stationary infrastructure and another to be run on the mobile device. At the hardware level, orchestrated resource-management strategies will be developed to enable designers to correctly design and implement highly resource-constrained embedded systems while helping them to meet system-level constraints. This requires augmenting today's functional design flows with a resource-centric view. Here, the goal is not to replace existing design methodologies with yet another all-encompassing methodology, but rather making a cross-cutting impact by demonstrating the applicability of results to several driving examples at different levels of abstraction, including System-on-Chip (SoC) platforms, memory architecture level, and operating system level.