Test Resource Partitioning and Optimization for System-on-a-Chip

Duke University, Durham NC

Investigators

Abstract

The goal of this research is to develop system-on-a-chip (SOC) test resource partitioning techniques based on test data compression. Topics being investigated under this grant include: (i) data compression codes; (ii) efficient on-chip decompression architectures; (iii) low-power scan testing. This project is expected to lead to a unified framework to reduce SOC test data volume, testing time, and test power.