NER: Nanochannel Field-Effect Transistors (FETs) and Quantum Dot Based Nonvolatile Memory Cells using Site-Specific and Layer-by-Layer Self-Assembly Techniques

University Of Connecticut, Storrs CT

Investigators

Abstract

NER Proposal #0210428 PI: Faquir Jain Nanochannel FETs and Quantum Dot based Nonvolatile Memory Cells using Site-Specific and Layer-by-Layer Self-Assembly Techniques Summary This proposal aims at forming nanochannels (10-30 nm length with ~100nm width), using SiOx-Si nanomasks deposited via site-specific self-assembly, to fabricate FETs with enhanced performance. In addition, it seeks to develop quantum dot based nonvolatile memory cell structures in floating gate and floating trap configurations. These nonvolatile memory cells are proposed to be grown using layer-by-layer self-assembly of ZnS-cladded CdSe or ZnCdSe quantum dots (with core diameter ~3-5nm). The final goal is the integration of FETs with nonvolatile memory cells to design programmable circuits.