Collaborative Research: Platform-Based CAD for Power and Performance Optimization

University Of California-Irvine, Irvine CA

Investigators

Abstract

As integrated circuit chips are becoming more complex to design, pre-fabricated platform chips, intended to meet the needs of a wide variety of embedded computing products, are becoming increasingly common. The trend towards platforms creates the need for parameterizing computing architectures such that platforms can have their performance and power consumption adapted to the different needs of different products, and that can be tuned to the particular compute patterns of a particular product. This project will investigate several aspects of such parameterization. It will demonstrate the feasibility of extensive parameterization of an architecture's memory components, key contributors to power and performance. It will define the basic tasks that make up platform-oriented CAD, partition computer-aided design (CAD) tasks between desktop and platform resources to yield fast yet accurate and cost-effective CAD solutions, and develop new CAD exploration algorithms for desktop/platform co-exploration. The research will benefit platform designers, who need an understanding of parameters and tuning issues to effectively build heavily parameterized platforms and their associated CAD tools, and platform users, who can utilize such platforms and CAD tools to develop more efficient platform-based designs than currently possible.