ITR: Code and Data Segment Optimizations for Mixed Width Instruction Set Embedded Processor

University Of Arizona, Tucson AZ

Investigators

Abstract

The ARM processor, a leading processor design for the embedded domain, supports a 32 bit ARM instruc-tion set as well as a 16 bit Thumb instruction set. This project is aimed at exploring two approaches for generating code that will simultaneously achieve the goals of small code size, low energy consumption, and good performance. The frst approach judiciously combines the use of ARM and Thumb instructions to generate mixed code either dynamically or at compile time. The second approach focusses on changing the data layout in a way that compact code can be generated without sacrifcing good performance. To thoroughly explore the above approaches an experimental infrastructure based upon the Simplescalar simulator and the gcc compiler is being developed.