ITR: Statically Speculative Power-Aware\(SPA)\Architectures

University Of Massachusetts Amherst, Amherst MA

Investigators

Abstract

This project focuses on compiler-enabled power-aware architectures. Its purpose is to leverage static program information in smart ways, to reduce power and energy consumption in both embeddded and general-purpose architectures. We follow three key general ideas to achieve this goal: (1) we use static information to throttle processor resources, (2) we incorporate architectural features to directly support static compiler managed modes of operation, and (3) we leverage speculative static information in addition to the predictable static information to support (1) and (2). We have demonstrated, in a number of processor architectural domains, that our approach is feasible, and can be easily implemented, and that considerable energy savings, beyond what would be possible with circuit and architectural techniques alone, can be achieved. We estimate that our techniques if combined, can give an additional 30% or more energy savings compared to state-of-the-art low-power designs, while not significantly affecting performance.