Information Encoding for Energy Efficient Processor Design

University Of Arizona, Tucson AZ

Investigators

Abstract

This project investigates the role of information encoding techniques for reducing energy consumed by various processor components including the fetch mechanism, on-chip instruction and data caches, functional units, instruction issue logic, and CPU I/O pins. To address energy consumption by all of the above processor components, three distinct types of encodings will be investigated in this project. Data encoding will be used to reduce the activity in data caches where the data resides and external data bus I/O pins over which data is transmitted. Instruction encodings in form of 32 bit ARM ISA and 16 bit Thumb ISA available in the XScale processor will be used to generate compact code which gives high performance. Finally, compiler or profiler generated hints will be encoded into the generated code to throttle the energy consumption of a processor.